Some embodiments described herein relate generally to mechanisms for accessing multiple memories, and, in particular, to methods and apparatus for efficiently scheduling requests to access multiple memories that share a common address bus or control interface.
Some memory systems use a single address bus or control interface to control each independent memory part. Such a mechanism is, however, typically not scalable to a large number of memory parts. Some other memory systems use a shared address bus or control interface across multiple independent memory parts. In such memory systems, the shared address bus or control interface is typically the bottleneck for processing workloads, and the performance of the memory systems is typically limited by the number of commands that can be issued on the shared address bus or control interface. Some of such memory systems access two independent memory parts in a strict time-division multiplexing (TDM) manner. Such a strict TDM scheduling scheme, however, typically results in substantially low performance when applied to memory systems with three or more independent memory parts.
Accordingly, a need exists for methods and apparatus that can efficiently schedule requests to access multiple (e.g., more than two) memory parts that share an address bus or control interface.